Without limiting the scope of the invention, its background is described in connection with resonant tunneling devices and methods for implementing multivalued logic operations.
Resonant Tunneling Devices
Within the last decade, heteroepitaxial technology has allowed researchers to explore the electrical properties of a variety of superlattice, quantum well, and resonant tunneling structures. The first proposals and investigations of the resonant tunneling diode were reported by Chang, Esaki, and Tsu (Applied Physics Letters, 24, p. 592) and subsequently given impetus by Sollner et al. (Applied Physics Letters, 43, p.588) who observed large negative differential resistance (hereinafter referred to as NDR) in these structures. Because only discrete energy states are available for charge transport through quantum wells, the current-voltage relationship of a resonant tunneling diode may exhibit a peak, i.e., for applied voltages increasing from zero, the diode current increases, then decreases for a range of larger applied voltages. Multiple peak resonant tunneling devices (hereinafter referred to as M-RTD) consisting of series combinations of RTDs in epitaxial stacks have also been demonstrated. Fifteen resonant peaks were achieved in a single heterostructure at room temperature recently fabricated at Texas Instruments.
Since the initial investigations of the RTD, many three-terminal resonant tunneling devices have been proposed and demonstrated (see, for example, F. Capasso, S. Sen and F. Beltram, High Speed Semiconductor Devices (S. M. Sze, ed.), p. 465, John Wiley & Sons, New York). Integration of RTDs into one or another of the terminals of conventional transistors has led to a large family of resonant tunneling transistors. Among the most promising of these transistors are: the resonant tunneling bipolar transistor (RTBT) (see, for example, F. Capasso, S. Sen, and A. Y. Cho, Applied Physics Letters, 51, p. 526); the resonant tunneling hot electron transistor (RHET) (see, for example, N. Yokoyama et al., Solid State Electronics, 31, p. 577); and the resonant tunneling field effect transistor (RTFET). These devices are fabricated by placing RTDs in the emitter terminals of heterojunction bipolar transistors, hot electron transistors or field effect transistors, respectively.
Nanoelectronic devices, such as resonant tunneling diodes and transistors, are under investigation in many laboratories for their potential to operate at dimensions much smaller than conventional transistors can function. The goal of these device designs is to harness the quantum effects themselves to allow scaling to dimensions on a nanometer scale. Examples of such nanoelectronic devices are described, for example, in:
U.S. Pat. No. 4,581,621, "Quantum Device Output Switch", issued Apr. 8, 1986, to Reed;
U.S. Pat. No. 4,704,622, "Negative Transconductance Device", issued Nov. 3, 1987, to Capasso et al.;
U.S. Pat. No. 4,721,983, "Three Terminal Tunneling Device", issued Jan. 26, 1988, to Frazier;
U.S. Pat. No. 4,849,799, "Resonant Tunneling Transistor", issued Jul. 18, 1989, to Capasso et al.;
U.S. Pat. No. 4,851,886, "Binary Superlattice Tunneling Device and Method", issued Jul. 25, 1989, to Lee et al.;
U.S. Pat. No. 4,853,753, "Resonant-Tunneling Device, and Mode of Device Operation", issued Aug. 1, 1989, to Capasso et al.;
U.S. Pat. No. 4,912,531, "Three-Terminal Quantum Device", issued Mar. 27, 1990, to Reed et al.;
U.S. Pat. No. 4,959,696, "Three Terminal Tunneling Device and Method", issued Sep. 25, 1990, to Frensley et al.; and
U.S. Pat. No. 4,999,697, "Sequential-Quenching Resonant-Tunneling Transistor", issued Mar. 12, 1991, to Capasso et al.
Multivalued Logic
Binary arithmetic integrated circuits (ICs) have enabled a revolution in the performance of embedded coprocessors and high-performance computers, but scaling limits will ultimately prevent further increases in the speed and density of conventional ICs. Soon after the year 2000, quantum mechanical effects will set fundamental limits on the scalability of conventional transistors (see, for example, R. T. Bate, Nanotechnology, 1, p. 1, 1990). Feature sizes less than approximately 0.1 .mu.m will cause leakage in conventional devices that will prevent scaling from increasing IC performance.
In the future, ultra-high performance digital systems will require clock rates in excess of 10 GHz with minimum data latency. Current systems, using binary computation based on silicon VLSI technology, can achieve reasonably good performance by using complex carry-ripple reduction schemes; however, data latency and ultra-fast computing requirements will make this approach unsuitable for certain classes of systems.
Multivalued Logic (hereinafter referred to as MVL) circuits have the potential for increased speed and density (for the same minimum feature geometry) since multiple binary bits may be simultaneously processed in a single MVL circuit. For examples of multivalued logic adders and multipliers which offer ripple-carry free operation through the use of redundant number systems, see, for example: L. J. Micheel, Proceedings of the International Symposium on MVL, 1992; J. Goto et al., International Solid State Circuits Conference, 1991; and M. Kameyama, M. Nomura and T. Higuchi, Proceedings of the International Symposium on MVL, 1990. To date, implementation of these approaches has been proposed based on conventional integrated circuit families (e.g. CMOS and heterojunction ECL).